(1) Field of the Invention
This invention relates to a fabrication method of a power semiconductor structure, and more particularly relates to a fabrication method of a power semiconductor with reduced gate impedance.
(2) Description of the Prior Art
Energy conservation is an important issue nowadays. The trend of energy conservation encourages the settlement of strict energy efficiency standards, which brings a severe challenge for the developers of power converters. To meet this challenge, the new power device, such as the power MOSFET, plays an important role and has been widely applied to various power converters.
FIGS. 1A to 1C are schematic cross-section views showing the fabrication method of a typical trenched power semiconductor structure. An N-type trenched power MOSFET is described below for example. As shown in FIG. 1A, firstly, an N-type silicon substrate 110 is provided, and then a mask (not shown) is utilized to define the location of gate trenches 120 in the silicon substrate 110. The gate trenches 120 are then formed in the N-type silicon substrate 110 by dry etching. Thereafter, a gate oxide layer 130,132 is formed on the exposed surfaces of the N-type silicon substrate 110.
Next, a polysilicon layer is deposited over the N-type silicon substrate 110 to fill the gate trenches 120. Then, the portion of the polysilicon layer on the upper surface of the N-type silicon substrate 120 is removed by etching back to leave a plurality of polysilicon gates 140 located in the gate trenches 120. Thereafter, as shown in FIG. 1B, a blanket ion implantation is carried out to implant P-type dopants in the N-type silicon substrate 110 to form a doped region 150. Then, as shown in FIG. 1C, the implanted P-type dopants are driven in the silicon substrate 110 by annealing so as to form a P-body 150′ in the N-type silicon substrate 110.
When scaling down the cell dimension of MOSFETs for a higher integration, the resistance of the polysilicon gate 140 is increased due to a narrower and shallower gate trench 120. The switching speed of the transistor would be badly influenced by the increased gate resistance and a greater switching loss is resulted.
The resistance of polysilicon material can be quite high, which is usually greater than 1 mΩ-cm, in respective with the metal material. In order to reduce the resistance of the polysilicon gate 140, a typical method is to form low resistance silicide on the polysilicon gate 140.
As to the fabrication process of typical self-aligned silicide (salicide), the timing of the fabrication step of the silicide layer should be postponed until the ion implantation steps and the thermal drive-in steps are finished, such that the unwanted diffusion of metal ions under high temperature to result in pollution can be prevented and the thickness of the silicide layer can be well-controlled. However, as shown in FIGS. 1B and 1C, the drive-in step is usually performed in oxygen ambient, which may result in the formation of the oxide layer on the surface of the polysilicon gate 140. In addition, the oxide layer 134 formed on the polysilicon gate 140 with high density dopants is always thicker than the oxide layer 132′ on the surface of the silicon substrate 120.
The oxide layers 134, 132′ may hinder the formation of silicide. Thus, as shown in FIG. 1C, to form self-aligned silicide (salicide), the oxide layer 134 on the polysilicon gate 140 should be removed but the oxide layer 132′ should be kept on the silicon substrate 110. However, as mentioned above, because the thickness of the oxide layer 134 on the polysilicon gate 140 is greater than the oxide layer 132′ on the silicon substrate 110, it is difficult to selectively remove the oxide layer 134 on the polysilicon gate 140 but leave the oxide layer 132′ on the silicon substrate 110 merely by etching.